This invention relates to controlling the flow of data between an operational circuit and a data storage circuit. In particular, but not exclusively, the operational circuit may be a device which uses the data storage circuit and the data storage circuit may be a memory.
In known systems using integrated circuits one of the areas which restricts the overall system performance is the interface between the memory device and the internal bus of an operational circuit which accesses that memory. A number of memory devices have been recently introduced which have improved data transfer rates in comparison to conventional memory devices. For example, conventional SDRAM (synchronous dynamic random access memory) typically has a data transfer rate of 32 bits at 100 MHz. An improvement to this is double data rate (DDR) SDRAM which is capable of transferring double the data rate than a conventional SDRAM and hence has a data transfer rate of 32 bits at 200 MHz. There are also available memory devices known as Direct Rambus memories (RDRAM Rambus Dynamic Random Access Memory) which have a transfer rate of 16 bits at 800 MHz. xe2x80x98Rambusxe2x80x99 and xe2x80x98Direct Rambusxe2x80x99 are trade marks of Rambus Inc.
Present conventional integrated circuits typically have an internal system bus with a data transfer rate of 32 bits at 100 MHz. FIG. 1 schematically illustrates a conventional integrated circuit 1 with an internal system bus 5 and three known memory devices, a conventional SDRAM 2, a double data rate SDRAM 3 and a Direct Rambus memory 4. (In practice only one of the three memory devices is provided). Each of the memory devices 2, 3 and 4 has an output bus which in use is coupled to the internal system bus 5 of the integrated circuit. The output bus 6 of the conventional SDRAM 2 has a data transfer rate of 32 bits at 100 MHz and is therefore entirely compatible with the internal bus 5 of the integrated circuit 1, which as shown, also has a data transfer rate of 32 bits at 100 MHz. However, the output bus 7 of the DDR SDRAM 3 has a data transfer rate of 32 bits at 200 MHz and the output bus 8 of the Direct Rambus memory 4 has a data transfer rate of 16 bits at 800 MHz. Accordingly the output buses 7 and 8 of the DDR SDRAM 3 and the Direct Rambus memory 4 are not compatible with the internal system bus 5 of the integrated circuit 1 in terms of data rate. Accordingly, with the existing conventional internal bus system of the integrated circuit, the higher data transfer rate of the DDR SDRAM and the Direct Rambus cannot be readily used.
To exploit the increased transfer rate of the faster memory devices, the width of the internal bus of the operational integrated circuit could be increased. For example, for a Direct Rambus memory with a transfer rate of 16 bits at 800 MHz, the internal bus of the operational integrated circuit would have to be increased to a 128 bit bus operating at 100 MHz. As this is four times the present conventional bus width the resulting integrated circuit would be much more complex and require increased effort in designing the layout of the interconnects within the integrated circuit and would also consume a much larger area of silicon. This is disadvantageous. FIG. 2 illustrates an example of a Direct Rambus 4 connected to an integrated circuit 1, the integrated circuit having an internal system bus 5 with a transfer rate of 128 bits at 100 MHz. At the interface between the Direct Rambus memory 4 and the integrated circuit 1, a demultiplexer 10 would be required to spread the short 16 bit words from the Direct Rambus onto the 128 bit wide internal bus of the integrated circuit. The addition of a demultiplexer 10 further increases the complexity and required silicon area of the integrated circuit.
The speed of the internal bus of the integrated circuit could be increased to match that of the memory device connected to it. However, this would require redesigning the integrated circuit and in practice, the internal buses of integrated circuits which represent the current state of the art already typically operate at a speed close to the current maximum possible speed.
It is an aim of embodiments of the present invention to provide an improved interface between data storage devices with a relatively high data transfer rate and the internal bus system of an integrated circuit operating with a relatively low data transfer which overcomes or at least mitigates against the problems described hereinbefore.
According to one aspect of the present invention there is provided circuitry for controlling a flow of data comprising: an operational circuit arranged to generate at least one data access request; data storage circuitry arranged to output or store data in response to receiving said at least one data access request signal; and buffer circuitry coupled between the operational circuitry and the data storage circuitry arranged to store said at least one data access request from the operational circuitry and store data from the data storage circuitry, wherein in use the number of stored data access request signals decreases as the amount of stored data from the data storage circuitry increases and the number of stored data access request signals increases as the amount of stored data from the data storage circuitry decreases.
According to a second aspect of the present invention there is provided a method for controlling flow of data comprising the steps: receiving data access request signals at the input of buffer circuitry; storing said data request signals in the buffer circuitry; receiving data at said input of the buffer circuitry; and storing said data in the buffer circuitry.